1. Field of the Invention
The present invention relates to a system for a digital synthesis of several different clock signals (DCS=digital clock synthesis), and in particular to a method and a device for generating a clock signal having predetermined clock signal properties, and here in particular to a method and to a device for generating a clock signal with almost any desired frequency and a desired duty cycle.
2. Description of the Related Art
Traditionally, independent clock signals are generated using the known analog clock synthesis, wherein conventionally a plurality of PLLs (PLL=phase locked loop) are used. Such traditional approaches are disadvantageous, as here the overall jitter contribution is high and the clock accuracy is limited, as conventional analog PLLs are limited to discrete frequencies which are admitted by the PLL divider elements. A further disadvantage of conventional approaches is, that the analog circuits used require a plurality of circuit blocks, so that the circuit complexity is high. Further, the number of PLLs that may be realized on a single chip is limited, and thus also the number of available independent clock signals. Again, a further disadvantage of conventional approaches is, that for each of the PLLs used with conventional analog approaches an associated external analog power supply must be provided. The design expense for analog circuits is high.
EP 1 137 188 A2 describes a digital PLL in which only individual pulses of a multi-phase clock are selected that control a toggle flipflop which then generates a clock having a 50% duty cycle. A “traditional” PLL-loop with a digital phase comparator is used. A phase comparison sync/synth.sync causes an iterative post-controlling of phase and frequency of the sample clock. It is not possible to generate (several) clocks with a binary programmable frequency, duty cycle and phase with any accuracy (not even integer) multiples of a sync clock.
U.S. Pat. No. 6,031,401 describes a clock signal synthesizer generating a time signal, which is a multiple of the frequency of a master clock signal. The synthesizer can programmably adjust the rising and falling edges of the synthesized wave form within the period of the master clock signal. The synthesizer has a delay line with several taps, which will generate repetitions of the master clock signal, which are incrementally delayed to the master clock signal. Part of the delay signals is provided as input signal to each of a plurality of multiplexers, wherein a delay signal is selected depending on a selection signal The selected delay signals are transmitted as input signals to flipflop circuits, the outputs of which are connected to a combinatorial logic, which will connect the signals from the outputs of the different flipflop circuits to generate the synthesized time signal.
U.S. Pat. No. 5,394,111 describes a programmable signal generator with a resolution of one nanosecond. The generator generates a clock signal having a frequency, a phase shift and a clock cycle, which is relative to a periodic reference signal. Therefore, the output signals of a voltage-controlled ring oscillator are used directly to drive the inputs of a programmable logic gate to generate pulses. The phase shift has a resolution of one nanosecond. Additionally, the generated pulses can be logically connected to generate clock signals with a multiple of the input frequency.